The present invention relates generally to a method for manufacturing transistors, and, more particularly, to a method for manufacturing a buried transistor in which the source/drain regions thereof are self-aligned with an insulating film formed on a channel region thereof.
A buried transistor is a transistor which is made by forming the source/drain regions thereof prior to forming the gate electrode thereof, in contrast to a conventional transistor, in which the gate electrode is formed first and then used as a mask for formation of the source/drain regions thereof. Among other applications, buried transistors are employed as the transistors constituting the cell array of read only memory devices (ROMs).
With reference now to FIGS. 1A-1G, a conventional method for manufacturing buried transistors of a semiconductor memory device (e.g., a ROM) will now be described.
With particular reference now to FIG. 1A, an N-well 12 and a P-well 14 are formed in a surface region of a semiconductor substrate 10 by using conventional CMOS twin well process technology. Next, a pad oxide film 16 is formed on the upper surface of the semiconductor substrate 10. Then, a silicon nitride (Si.sub.3 N.sub.4) film 18 is deposited on the pad oxide film 16. Next, a photoresist layer is formed on the silicon nitride film 18, and then patterned, to thereby provide a patterned photoresist mask 20 having apertures over regions of the substrate 10 where field oxide regions are to be subsequently formed. Then, the portions of the pad oxide film 16 and silicon nitride film 18 underlying the apertures in the photoresist mask 20 are etched away, to thereby expose portions of the upper surface of the semiconductor substrate 10 corresponding to the regions where the field oxide regions are to be subsequently formed.
With particular reference now to FIG. 1B, the photoresist mask 20 is removed, and a patterned photoresist mask 22 is formed on the resultant structure. Next, boron ions are ion-implanted in the exposed surface regions of the semiconductor substrate 10, to thereby form channel stop regions 24 in the P-well 14.
With particular reference now to FIG. 1C, the photoresist mask 22 is removed, and the resultant structure is exposed to an oxide atmosphere, to thereby form field oxide regions 26 in the surface regions of both the N-well 12 and the P-well 14. Next, impurities are ion-implanted in the resultant structure to control the threshold voltage of the transistors to be subsequently formed in the N-well 12 and the P-well 14.
With particular reference now to FIG. 1D, a patterned photoresist mask 28 is formed on the resultant structure depicted in FIG. 1C, and source/drain regions 30 separated from one another by a distance "L" are formed in the cell region of the P-well 14, by ion-implanting N-type impurities into the surface region of the P-well 14, using the photoresist mask 28 as an ion-implantation mask.
With particular reference now to FIG. 1E, the photoresist mask 28 is removed, and a patterned photoresist mask 32 is formed on the resultant structure. The photoresist mask 32 exposes only the cell region of the resultant structure. Next, impurities are ion-implanted in the cell region of the P-well 14 to control the threshold voltage of transistors to be formed in the cell region of the P-well 14, using the photoresist mask 32 as an ion-implantation mask.
With particular reference now to FIG. 1F, the photoresist mask 32 is removed, and a gate insulation film 34 and a gate electrode layer are sequentially formed on the resultant structure. Next, a patterned photoresist mask 38 is formed on the resultant structure. Then, the gate electrode layer is etched, using the photoresist mask 38 as an etching mask, to thereby form gate electrodes 36. At this stage of the process, the NMOS memory cell transistors formed in the cell region of the P-well 14 are completed.
With particular reference now to FIG. 1G, the photoresist mask 38 is removed, and sidewall spacers 40 are formed on the sidewalls of the gate electrodes 36 in the PMOS and NMOS regions of the device. Next, lightly doped source/drain (LDD) regions 42 are formed in the N-well 12 and the P-well 14 on opposite sides of the gate electrodes 36 in the PMOS and NMOS regions of the device, to thereby provide a PMOS transistor in the N-well 12 and an NMOS transistor in the P-well 14.
As can be appreciated on the basis of the foregoing description, the source/drain regions of a buried transistor manufactured in accordance with the conventional technology are formed prior to formation of the gate electrode thereof. Consequently, the length "L" of the channel region of the buried transistors formed in the cell region of the semiconductor memory device is determined by the geometries of the photoresist mask 28, and the width of the channel region of the buried transistors formed in the cell region of the device is determined by the width of the gate electrode 36.
With additional reference now to FIG. 2, which is an enlarged view of a portion of the device enclosed by a dotted circle II in FIG. 1G, the reference numeral 3 designates the portion of the source/drain regions 30 which is present before the gate insulation film 34 is formed, the reference numeral 6 designates extended portions (OED regions) of the source/drain regions 30 which are formed after the gate insulation film 34 is formed, reference numeral 4 designates relatively thin portions of the gate insulation film 34 formed on channel regions of the buried transistors formed in the P-well 14, reference numeral 5 designates relatively thick portions of the gate insulation film 34 formed on the source/drain regions 30 of the buried transistors formed in the P-well 14, reference numeral 8 designates the encircled channel stop layer 24, reference numeral 7 designates the encircled field oxide region 26, and the reference numeral 9 designates the encircled portion of the gate electrode 36 formed on the cell region of the P-well 14. It can be seen that the effective channel length 1 of the buried transistors formed in the P-well 14 is shortened (and the effective length 2 of the source/drain regions 30 lengthened) due to the formation of the extended portions 6 of the source/drain regions 30 as a consequence of the formation of the gate insulation film 34, which lowers the punch-through voltage of the buried transistors formed in the cell region of the P-well 14.
In general, the punch-through characteristics of the buried transistors manufactured in accordance with the conventional method are degraded for the following three principal reasons.
First, the process steps for forming the gate insulation film 34 and the gate electrodes 36, and subsequent process steps for forming a high temperature oxide (HTO) layer (not shown) and a re-flowed BPSG layer (not shown), which are performed after the source/drain regions 30 are formed, thermally diffuse the source/drain regions 30 in a lateral direction, thereby reducing the effective channel length of the buried transistors, and thus, the punch-through voltage thereof.
Second, due to damage to the crystal structure of the source/drain regions 30 as a result of the ion-implantation process, the portions of the gate insulation film 34 on the source/drain regions 30 have a greater thickness than the portions of the gate insulation film 34 on the channel regions therebetween. In this connection, impurities (e.g., arsenic or phosphorus ions) constituting the source/drain regions 30 combine more easily with silicon than with oxide. Consequently, the oxidation enhanced diffusion (OED) regions 6 are formed at the boundaries between the channel region and the source/drain regions of the buried transistors when the gate insulation film 34 is formed, thereby significantly extending the effective length of the source/drain regions 30 of the buried transistors, and, conversely, significantly reducing the effective channel length of the buried transistors.
Third, due to resolution limitations of the photolithographic equipment employed in manufacturing high integration density devices having half-micron (or less) geometries (i.e., .ltoreq.0.5 .mu.m design rule), the channel length "L" of the buried transistors tends to be shorter and less uniform than desired, thereby further degrading the performance and punch-through voltage characteristics of the buried transistors manufactured in accordance with the conventional technology.
Based on the above, it can be appreciated that there presently exists a need in the art for a method for manufacturing a buried transistor which overcomes the above-described drawbacks and shortcomings of the conventional technology. The present invention fulfills this need.